LONDON--Spin-torque transfer magnetic RAM (STT-MRAM) is leading a race for inclusion as an embedded non-volatile memory at the 28nm chip production node according to Arnaud Furnemont, memory department director for research institute IMEC.
memory (PCM) have their supporters these memory types have problems with scaling & can be hard to accommodate in 28nm CMOS, Furnemont told EE Times Europe during the recent IMEC Technology Forum held in Brussels.
The 28nm planar CMOS node is expected to be long-lived & to accommodate a great deal of More-than-Moore developments but to do this it requires a non-volatile memory option & flash memory does not scale effectively.
There are a large number of material systems vying to be the basis of a resistive RAM but most of these are based on the making & breaking of a conducting filament at conductor cross-point. & therein lies the problem at least for achieving large arrays as might be used in st&-alone memories
Filamentary ReRAMs do not scale, said Furnemont. "Because you always end up with single filament & that requires about 100-microamperes for a stable filament. As you scale the cross-point the power doesn't reduce," he said.
While the exact current may vary between material systems the other side of this coin is that as the array size increases the power consumption increases with the number of bit cells in the array.
IMEC has studied hafnium oxide & tantalum oxide ReRAMs in depth. Furnemont said there are some possibilities for ReRAM at 20nm but because it doesn't scale would represent expensive engineering that is probably only good for a single node. "It may be good for embedded but not for st&-alone memory," said Furnemont.
PCM is an alterntive where the memory still forms around an original filament but which involves a thermally-induced phase change in a volume of material. The size of this material volume & the current does appear to scale making it a more promising option; one that could go down to 10nm in Furnemont's opinion.
MRAM is his favourite for inclusion at 28nm partly for economic reasons; because it can be implemented in as few as three extra masks. In addition it is compatible with CMOS voltage schemes & does not require charge pumps
Although the MRAM can be essentially created in the back-end of line it does need to be a driven by a transistor implemented in the bulk so it can be implemented "area-free," he said.
